View SH69P26_7146668.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SH69P26 otp 6k 4-bit micro-controller v2.2 1 features sh6610d-based single-chip 4-bit micro-controller otprom: 6k x 16 bits ram: 389 x 4 bits - 69 system control register - 320 data memory operation voltage: - f osc = 30khz - 4mhz, v dd = 2.4v - 5.5v - f osc = 4mhz - 8mhz, v dd = 4.5v - 5.5v 29 cmos bi-directional i/o pins 8-level stack (including interrupts) two 8-bit auto re-loaded timer/counter, one can switch to external clock source warm-up timer built-in pull-high for i/o port powerful interrupt sources: - timer0 interrupt - timer1 interrupt - timer2 interrupt - external interrupts: portf (falling edge), cmpout oscillator (code option) - crystal oscillator: 32.768khz, 400khz - 8mhz - ceramic resonator: 400khz - 8mhz - external rc oscillator: 400khz - 8mhz - internal rc oscillator: 2mhz, 4mhz, 6mhz - external clock: 30khz - 8mhz instruction cycle time (4/f osc ) two low power operation modes: halt and stop reset: - built-in watchdog timer (code option) - built-in power-on reset (por) - built-in low voltage reset (lvr) two-level low voltage reset (lvr) (code option) one 16-bit timer/counter for pulse measurement led numeric display drive capability on porta, portb, portd and porth [1:0] built-in one comparator read rom table function 2 channels tone generator internal reliable reset circuit otp type/code protection 28-pin skinny/28-pin sop/32-pin dip package general description the SH69P26 is a single-chip 4-bit micro-controller. this dev ice integrates a sh6610d cpu core, 6k words of otprom, 389 nibbles of ram, two 8-bit ti mer/counter and one 16-bit timer/counter, compar ator, two channel tone generators, on-chip oscillator clock circuitry, on-chip watchdog timer, low volt age reset function. the SH69P26 is suitable for microwave oven application. free datasheet http:///
SH69P26 2 pin configuration (32-lead dip package) (28-lead skinny/sop package) SH69P26 /32pin portg.2/cmpp4 portg.3/cmpp3 porte.3/cmpp2 porte.2/cmpp1 porte.1/cmpn porte.0/cmpout portc.2/t0 gnd porta.0 porta.1 porta.2 porta.3 portd.0 portd.1 porth.0 porth.1 portb.1 portb.0 portd.3 portd.2 osci/portc.0 v dd portb.3 portb.2 portf.2 portf.1/t2 portf.0/tone osco/portc.1 portg1/cmpp5 portg.0/cmpp6 portf.3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 reset SH69P26 /28pin porte.3/cmpp2 porte.2/cmpp1 porte.1/cmpn porte.0/cmpout portc.2/t0 gnd porta.0 porta.1 porta.2 porta.3 portd.0 portd.1 porth.0 porth.1 portb.1 portb.0 portd.3 portd.2 osci/portc.0 v dd portb.3 portb.2 portf.2 portf.1/t2 portf.0/tone osco/portc.1 portf.3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 reset free datasheet http:///
SH69P26 3 block diagram oscillator cpu wdt rc portc (1 bit) portg (4 bits) otp rom 6144 x 16 bits ram 69 x 4 bits system register timer 0 (8 bits) watchdog timer porte (4 bits) reset circuit timer2 (16 bits) osci/portc.0 osco/portc.1 v dd gnd reset porta (4 bits) portb (4 bits) portb.0 portb.1 portb.2 portb.3 ram 320 x 4 bits data memory power circuit portc.2/t0 portd.0 porta.0 porta.1 porta.2 porta.3 portc (2 bits) portf (4 bits) porth (2 bits) portd (4 bits) portd.1 portd.2 portd.3 comparator porte.0/cmpout porte.1/cmpn porte.2/cmpp1 porte.3/cmpp2 portf.0/tone portf.1/t2 portf.2 portf.3 portg.0/cmpp6 portg.1/cmpp5 portg.2/cmpp4 portg.3/cmpp3 porth.0 porth.1 tone generator1 tone generator2 timer1 (8 bits) free datasheet http:///
SH69P26 4 pin description pin no. 32-pin dip 28-pin skinny/sop designation i/o description 1 - portg.2 /cmpp4 i/o i bi-directional i/o port shared with comparator positive input 4 2 - portg.3 /cmpp3 i/o i bi-directional i/o port shared with comparator positive input 3 3 1 porte.3 /cmpp2 i/o i bi-directional i/o port shared with comparator positive input 2 4 2 porte.2 /cmpp1 i/o i bi-directional i/o port shared with comparator positive input 1 5 3 porte.1 /cmpn i/o i bi-directional i/o port shared with comparator negative input 6 4 porte.0 /cmpout i/o o bi-directional i/o port shared with comparator output 7 5 portc.2 /t0 i/o i bi-directional i/o port shared with timer0 external clock input 8 6 reset /portc3 i i/o reset pin input (low active) bi-directional i/o port (open-drain output) 9 7 gnd p ground pin 10 8 porta.0 i/o bi-directional i/o port 11 9 porta.1 i/o bi-directional i/o port 12 10 porta.2 i/o bi-directional i/o port 13 11 porta.3 i/o bi-directional i/o port 14 12 portd.0 i/o bi-directional i/o port 15 13 portd.1 i/o bi-directional i/o port 16 14 porth.0 i/o bi-directional i/o port 17 15 porth.1 i/o bi-directional i/o port 18 16 portd.2 i/o bi-directional i/o port 19 17 portd.3 i/o bi-directional i/o port 20 18 portb.0 i/o bi-directional i/o port 21 19 portb.1 i/o bi-directional i/o port 22 20 portb.2 i/o bi-directional i/o port 23 21 portb.3 i/o bi-directional i/o port 24 22 v dd p power supply pin 25 23 osci /portc.0 i i/o oscillator input pin, connect to crystal/ceramic oscillator or external resistor of external rc oscillator. shared with bi-directional i/o port in the internal rc oscillator code option free datasheet http:///
SH69P26 5 pin description (continued) pin no. 32-pin dip 28-pin skinny/sop designation i/o description 26 24 osco /portc.1 o i/o oscillator output pin, connect to crystal/ceramic oscillator shared with bi-directional i/o port in the rc oscillator code option 27 25 portf.0 /tone i/o i o bi-directional i/o port vector port interrupt. (falling edge active) shared with tone generator output 28 26 portf.1 /t2 i/o i i bi-directional i/o port vector port interrupt. (falling edge active) shared with timer2 external clock input 29 27 portf.2 i/o i bi-directional i/o port vector port interrupt. (falling edge active) 30 28 portf.3 i/o i bi-directional i/o port vector port interrupt. (falling edge active) 31 - portg.0 /cmpp6 i/o i bi-directional i/o port shared with comparator positive input6 32 - portg.1 /cmpp5 i/o i bi-directional i/o port shared with comparator positive input5 otp programming pin description (otp program mode) pin no. 32-pin dip 28-pin skinny/sop symbol i/o sharing description 24 22 v dd p v dd programming power supply (+5.5v) 8 6 v pp p reset programming high voltage power supply (+11v) 9 7 gnd p gnd ground 25 23 sck i osci programming clock input pin 10 8 sda i/o porta.0 programming data pin free datasheet http:///
SH69P26 6 function description 1. cpu the cpu contains the followin g functional blocks: program counter (pc), arithmetic logic unit (alu), carry flag (cy), accumulator, table branch register, data pointer (inx, dph, dpm, and dpl) and stacks. 1.1. pc the pc is used for rom addressing consisting of 12-bit: page register (pc11), and ripple carry counter (pc10, pc9, pc8, pc7, pc6, pc5, pc4, pc3, pc2, pc1, pc0). the program counter is loaded with data corresponding to each instruction. the unconditional jump instruction (jmp) can be set at 1-bit page regist er for higher than 2k. the program counter cans only 4k program rom address. (refer to the rom description). 1.2. alu and cy the alu performs arithmetic and logic operations. the alu provides the following functions: binary addition/subtraction (adc, sbc, add, sub, adi, sbi) decimal adjustments for addition/subtraction (daa, das) logic operations (and, eor, or, andim, eorim, orim) decisions (ba0, ba1, ba2, ba3, baz, bnz, bc, bnc) logic shift (shr) the carry flag (cy) holds the alu overflow that the arithmetic operation generates. during an interrupt service or call instruction, the carry flag is pushed into the stack and recovered from the stack by the rtni instruction. it is unaffected by the rtnw instruction. 1.3. accumulator (ac) the accumulator is a 4-bit regist er holding the results of the arithmetic logic unit. in conjun ction with the alu, data is transferred between the accumulator and system register, or data memory can be performed. 1.4. table branch register (tbr) table data can be stored in program memory and can be referenced by using table branch (tjmp) and return constant (rtnw) instructions. the tbr and ac are placed by an offset address in program rom. tjmp instruction branch into address ((pc11 - pc8) x (2 8 ) + (tbr, ac)). the address is determined by rtnw to return look-up value into (tbr, ac). rom code bit7-bit4 is placed into tbr and bit3-bit0 into ac. 1.5. data pointer the data pointer can indirectly address data memory. pointer address is located in register dph (3-bit), dpm (3-bit) and dpl (4-bit). the addressing range can have 3ffh locations. pseudo index address (inx) is used to read or write data memory, then ra m address bit9 - bit0 which comes from dph, dpm and dpl. 1.6. stack the stack is a group of registers used to save the contents of cy & pc (11-0) sequentially with each subroutine call or interrupt. the msb is saved for cy and it is organized into 13 bits x 8 levels. the stack is operated on a first-in, last-out basis and returned sequentially to the pc with the return instructions (rtni/rtnw). note: the stack nesting includes both subroutine calls and interrupts requests. the maximum allowed for subroutine calls and interrupts are 8 levels. if the number of calls and interrupt requests exceeds 8, then the bottom of stack will be shifted out, that program execution may enter an abnormal state. 2. ram built-in ram contains general-purpose data memory and system r egister. because of its static nature, the ram can keep data after the cpu enters stop or halt. 2.1. ram addressing data memory and system register can be accessed in one instruct ion by direct addressing. the following is the memory allocation map: system register and i/o: $000 - $02f, $380 - $394 data memory: $030 - $16f 2.2. configuration of system register address bit3 bit2 bit1 bit0 r/w remarks $00 iet0 iet1 iet2 iep r/w interrupt enable flags $01 irqt0 irqt1 irqt2 irqp r/w interrupt request flags $02 t0s t0m.2 t0m.1 t0m.0 r/w bit2-0: timer0 mode register bit3: t0 signal source $03 t0e t1m.2 t1m.1 t1m.0 r/w bit2-0: timer1 mode register bit3: t0 signal edge $04 t0l.3 t0l.2 t0l.1 t0l.0 r/w timer0 load/counter register low nibble $05 t0h.3 t0h.2 t0h.1 t0h.0 r/w timer 0 load/counter register high nibble $06 t1l.3 t1l.2 t1l.1 t1l.0 r/w timer1 load/counter register low nibble $07 t1h.3 t1h.2 t1h.1 t1h.0 r/w timer 1 load/counter register high nibble free datasheet http:///
SH69P26 7 configuration of system register (continued) address bit3 bit2 bit1 bit0 r/w remarks $08 pa.3 pa.2 pa.1 pa.0 r/w porta $09 pb.3 pb.2 pb.1 pb.0 r/w portb $0a pc.3 pc.2 pc.1 pc.0 r/w portc $0b pd.3 pd.2 pd.1 pd.0 r/w portd $0c pe.3 pe.2 pe.1 pe.0 r/w porte $0d pf.3 pf.2 pf.1 pf.0 r/w portf $0e tbr.3 tbr.2 tbr.1 tbr.0 r/w table branch register $0f inx.3 inx.2 inx.1 inx.0 r/w pseudo index register $10 dpl.3 dpl.2 dpl.1 dpl.0 r/w d ata pointer for inx low nibble $11 - dpm.2 dpm.1 dpm.0 r/w data poi nter for inx middle nibble $12 - dph.2 dph.1 dph.0 r/w data pointer for inx high nibble $13 cmpe cmpso cmpsn cmpen r/w comparator control register $14 cmpgo cmpsp2 cmpsp1 cmpsp0 r/w co mparator status register $15 t2go dec tm2s1 tm2s0 r/w bit1-0: set timer2 mode bit2: select directive edge active enable bit3: set timer2 function start $16 pacr.3 pacr.2 pacr.1 pacr.0 r/w porta input/output control $17 pbcr.3 pbcr.2 pbcr.1 pbcr.0 r/w portb input/output control $18 pccr.3 pccr.2 pccr.1 pccr.0 r/w portc input/output control $19 pdcr.3 pdcr.2 pdcr.1 pdcr.0 r/w portd input/output control $1a pecr.3 pecr.2 pecr.1 pecr.0 r /w porte input/output control $1b pfcr.3 pfcr.3 pfcr.1 pfcr.0 r/w portf input/output control $1c lvr t2e t2sc - r/w bit1: select external signal source for timer2 bit2: timer2 external signal source edge bit3: low voltage reset flag (read and write 0 only) $1d - - - - - reserved $1e - wdt wdt.2 - wdt.1 - wdt.0 - r/w r bit2-0: watchdog timer control bit3: watchdog timer overflow flag (read only) $1f - - - bnk0 r/w bit0: bank register for rom $20 pgcr.3 pgcr.2 p gcr.1 pgcr.0 r/w portg input/output control in 28 pin mode, all bits of this ram are reserved, always keep it to ?1? in the user?s program. refer to i/o notice $21 - - phcr.1 phcr.0 r/w porth input/output control $22 pg.3 pg.2 pg.1 pg.0 r/w portg in 28 pin mode, all bits of th is ram are reserved, always keep it to ?0? in the user?s program. refer to i/o notice $23 - - ph.1 ph.0 r/w porth $24 ppacr.3 ppacr.2 ppacr.1 ppacr.0 r/w porta pull high control $25 ppbcr.3 ppbcr.2 ppbcr.1 ppbcr.0 r/w portb pull high control $26 - ppccr.2 ppccr.1 ppccr.0 r/w portc pull high control $27 ppdcr.3 ppdcr.2 ppdcr.1 ppdcr.0 r /w portd pull high control $28 ppecr.3 ppecr.2 ppecr.1 ppecr.0 r/w porte pull high control $29 ppfcr.3 ppfcr.2 ppfcr.1 ppfcr.0 r /w portf pull high control free datasheet http:///
SH69P26 8 configuration of system register (continued) address bit3 bit2 bit1 bit0 r/w remarks $2a ppgcr.3 ppgcr.2 ppgcr.1 ppgcr.0 r/w portg pull high control $2b - - pphcr.1 pphcr.0 r/w porth pull high control $2c tv1.3 tv1.2 tv1.1 tv1.0 r/w tone generator 1 volume low nibble $2d tg1en tv1.6 tv1.5 tv1.4 r/w tone generator 1 volume high nibble tg1en: tone generator 1 enable $2e tv2.3 tv2.2 tv2.1 tv2.0 r/w tone generator 2 volume low nibble $2f tg2en tv2.6 tv2.5 tv2.4 r/w tone generator 2 volume high nibble tg2en: tone generator 2 enable $380 rdt.3 rdt.2 rdt.1 rdt.0 r/w rom data table address/data register $381 rdt.7 rdt.6 rdt.5 rdt.4 r/w rom data table address/data register $382 rdt.11 rdt.10 rdt.9 rdt.8 r/w rom data table address/data register $383 rdt.15 rdt.14 rdt.13 rdt.12 r/w ro m data table address/data register $384 t2d.3 t2d.2 t2d.1 t2d.0 r/w timer2 load/counter register (low nibble) $385 t2d.7 t2d.6 t2d.5 t2d.4 r/w timer2 l oad/counter register (middle_l nibble) $386 t2d.11 t2d.10 t2d.9 t2d.8 r/w timer2 load/counter register (middle_h nibble) $387 t2d.15 t2d.14 t2d.13 t2d.12 r/w timer 2 load/counter register (high nibble) $388 tg1.3 tg1.2 tg1.1 tg1.0 r/w tone generator 1 low nibble $389 tg1.7 tg1.6 tg1.5 tg1.4 r/w tone generator 1 middle nibble $38a tg1.11 tg1.10 tg1.9 tg1.8 r/w tone generator 1 high nibble $38b tg2.3 tg2.2 tg2.1 tg2.0 r/ w tone generator 2 low nibble $38c tg2.7 tg2.6 tg2.5 tg2.4 r/w tone generator 2 middle nibble $38d tg2.11 tg2.10 tg2.9 tg2.8 r/w tone generator 2 high nibble $38e - t2sc.2 t2sc.1 t2sc.0 r/w bit 2-0: timer2 prescaler register $38f - cnf2 - cnf1 - cnf0 cmpod - r r/w cmpod: comparator output data cnf2-0: select comparator input channel $390 pfien.3 pfien.2 pfien.1 pfien.0 r/w portf interrupt enable flags $391 - - - - - reserved $392 pfif.3 pfif.2 pfif.1 pfif.0 r/w portf interrupt request flags $393 - - - - - reserved $394 - - cmpif cmpie r/w bit0: cmp output interrupt enable flag bit1: cmp output interrupt request flag free datasheet http:///
SH69P26 9 3. rom the rom can address 6144 x 16 bits of program area from $000 to $17ff. 3.1. vector address area ($000 to $004) the program is sequentially executed. there is an area addre ss $000 through $004 that is reserved for a special interrupt service routine such as starting vector address. address instruction remarks $000 jmp* jump to reset service routine $001 jmp* jump to timer0 interrupt service routine $002 jmp* jump to timer1 interrupt service routine $003 jmp* jump to timer2 interrupt service routine $004 jmp* jump to portf or cmp service routine *jmp instruction can be replaced by any instruction. 3.2. rom data read table (rdt) system register: address bit3 bit2 bit1 bit0 r/w remarks $380 rdt.3 rdt.2 rdt.1 rdt.0 r/w rom da ta table address/data register $381 rdt.7 rdt.6 rdt.5 rdt.4 r/w rom da ta table address/data register $382 rdt.11 rdt.10 rdt.9 rdt.8 r/w rom da ta table address/data register $383 rdt.15 rdt.14 rdt.13 rdt.12 r/w rom data table address/data register the rdt register consists of a 13-bit write-only pc address l oad register (rdt.12 - rdt.0) a nd a 16-bit read-only rom table data read-out register (rdt.15 - rdt.0). to read out the rom table data, users should write the rom tabl e address to rdt register first (high nibble first then low nibble), then after one instruction, the right data will put into rdt register automatically (write lowest nibble of address in to $380 will start the data read-out action). 3.3. bank switch mapping program counter (pc11 - pc0) can only address 4k rom space. the bank switch technique is used to extend the cpu address space. the lower 2k of the cpu addressing space maps to the lower 2k of rom space (bank.0). the upper 2k of the cpu addressing space maps to one of the two ban ks (bnk.0 = $00 - $01) of the upper 4k of rom. the bank switch mapping is as follows: rom space cpu address bnk = $00 bnk = $01 $000 - $7ff $0000 - $07ff (bank 0) $0000 - $07ff (bank 0) $800 - $fff $0800-$0fff (bank 1) $1000 - $17ff (bank 2) free datasheet http:///
SH69P26 10 4. initial state 4.1. system register state: address bit3 bit2 bit1 bit0 power-on reset/pin reset wdt reset/low voltage reset $00 iet0 iet1 iet2 iep 0000 0000 $01 irqt0 irqt1 irqt2 irqp 0000 0000 $02 t0s t0m.2 t0m.1 t0m.0 0000 uuuu $03 t0e t1m.2 t1m.1 t1m.0 0000 uuuu $04 t0l.3 t0l.2 t0l.1 t0l.0 xxxx xxxx $05 t0h.3 t0h.2 t0h.1 t0h.0 xxxx xxxx $06 t1l.3 t1l.2 t1l.1 t1l.0 xxxx xxxx $07 t1h.3 t1h.2 t1h.1 t1h.0 xxxx xxxx $08 pa.3 pa.2 pa.1 pa.0 0000 0000 $09 pb.3 pb.2 pb.1 pb.0 0000 0000 $0a - pc.2 pc.1 pc.0 -000 -000 $0b pd.3 pd.2 pd.1 pd.0 0000 0000 $0c pe.3 pe.2 pe.1 pe.0 0000 0000 $0d pf.3 pf.2 pf.1 pf.0 0000 0000 $0e tbr.3 tbr.2 tbr.1 tbr.0 xxxx uuuu $0f inx.3 inx.2 inx.1 inx.0 xxxx uuuu $10 dpl.3 dpl.2 dpl.1 dpl.0 xxxx uuuu $11 - dpm.2 dpm.1 dpm.0 -xxx -uuu $12 - dph.2 dph.1 dph.0 -xxx -uuu $13 cmpe cmpso cmpsn cmpen 0000 uuuu $14 cmpgo cmpsp2 cmpsp1 cmpsp0 0000 0uuu $15 t2go dec tm2s1 tm2s0 0000 0uuu $16 pacr.3 pacr.2 pacr.1 pacr.0 0000 0000 $17 pbcr.3 pbcr.2 pbcr.1 pbcr.0 0000 0000 $18 - pccr.2 pccr.1 pccr.0 -000 -000 $19 pdcr.3 pdcr.2 pdcr.1 pdcr.0 0000 0000 $1a pecr.3 pecr.2 pecr.1 pecr.0 0000 0000 $1b pfcr.3 pfcr.2 pfcr.1 pfcr.0 0000 0000 $1c lvr t2e t2sc - 000- *uu- $1d - - - - ---- ---- $1e wdt wdt.2 wdt.1 wdt.0 0000 #000 $1f - - - bnk0 ---0 ---0 $20 pgcr.3 pgcr.2 pgcr.1 pgcr.0 0000 0000 $21 - - phcr.1 phcr.0 --00 --00 $22 pg.3 pg.2 pg.1 pg.0 0000 0000 $23 - - ph.1 ph.0 --00 --00 $24 ppacr.3 ppacr.2 ppacr.1 ppacr.0 0000 0000 $25 ppbcr.3 ppbcr.2 ppbcr.1 ppbcr.0 0000 0000 $26 - ppccr.2 ppccr.1 ppccr.0 -000 -000 $27 ppdcr.3 ppdcr.2 ppdcr.1 ppdcr.0 0000 0000 $28 ppecr.3 ppecr.2 ppecr.1 ppecr.0 0000 0000 free datasheet http:///
SH69P26 11 system register state: (continued) address bit3 bit2 bit1 bit0 power-on re set/pin reset wdt reset/low voltage reset $29 ppfcr.3 ppfcr.2 ppfcr.1 ppfcr.0 0000 0000 $2a ppgcr.3 ppgcr.2 ppgcr.1 ppgcr.0 0000 0000 $2b - - pphcr.1 pphcr.0 --00 --00 $2c tv1.3 tv1.2 tv1.1 tv1.0 xxxx uuuu $2d tg1en tv1.6 tv1.5 tv1.4 xxxx uuuu $2e tv2.3 tv2.2 tv2.1 tv2.0 xxxx uuuu $2f tg2en tv2.6 tv2.5 tv2.4 xxxx uuuu $380 rdt.3 rdt.2 rdt.1 rdt.0 xxxx uuuu $381 rdt.7 rdt.6 rdt.5 rdt.4 xxxx uuuu $382 rdt.11 rdt.10 rdt.9 rdt.8 xxxx uuuu $383 rdt.15 rdt.14 rdt.13 rdt.12 xxxx uuuu $384 t2d.3 t2d.2 t2d.1 t2d.0 xxxx xxxx $385 t2d.7 t2d.6 t2d.5 t2d.4 xxxx xxxx $386 t2d.11 t2d.10 t2d.9 t2d.8 xxxx xxxx $387 t2d.15 t2d.14 t2d.13 t2d.12 xxxx xxxx $388 tg1.3 tg1.2 tg1.1 tg1.0 xxxx uuuu $389 tg1.7 tg1.6 tg1.5 tg1.4 xxxx uuuu $38a tg1.11 tg1.10 tg1.9 tg1.8 xxxx uuuu $38b tg2.3 tg2.2 tg2.1 tg2.0 xxxx uuuu $38c tg2.7 tg2.6 tg2.5 tg2.4 xxxx uuuu $38d tg2.11 tg2.10 tg2.9 tg2.8 xxxx uuuu $38e - t2sc.2 t2sc.1 t2sc.0 -000 -uuu $38f - cnf2 - cnf1 - cnf0 cmpod - 0000 uuu0 $390 pfien.3 pfien.2 pfien.1 pfien.0 0000 0000 $391 - - - - ---- ---- $392 pfif.3 pfif.2 pfif.1 pfif.0 0000 0000 $393 - - - - ---- ---- $394 - - cmpif cmpie --00 --00 legend: x = unknown, u = unchanged, - = unimplemented read as ?0?. *, #: for the detail information, refer to the following table: symbol wdt reset lvr reset wdt reset & lvr reset power-on reset/pin reset * 0 1 1 0 # 1 0 1 0 4.2. others initial state: others after any reset program counter (pc) $000 cy undefined accumulator (ac) undefined data memory undefined free datasheet http:///
SH69P26 12 5. system clock and oscillator the oscillator generates the basic clock pulses that provid e the system clock to supply cpu and on-chip peripherals. system clock = f osc /4. 5.1. instruction cycle time: (1) 4/32.768khz ( 122.1 s) for 32.768khz oscillator. (2) 4/8mhz (= 0.5 s) for 8mhz oscillator. 5.2. oscillator type (1) crystal oscillator: 32.768khz or 400khz - 8mhz osci osco c1 c2 crystal 12pf (for reference only) 12pf (for reference only) (2) ceramic resonator: 400khz - 8mhz 30pf (for reference only) 30pf (for reference only) osci osco c1 c2 ceramic (3) rc oscillator: 400khz - 8mhz osci r osc v dd 1000pf (for reference only) external r osc rc osci/portc.0 osco/portc.1 internal r osc rc (f osc = 2mhz or 4mhz or 6mhz) (4) external input clock: 30khz - 8mhz osci external clock source osco/portc.1 note: - if the rc oscillator or the external input clock is selected, osco pin is used as the i/o port (portc.1). - if the internal rc oscillator is selected, osco pin is used as the i/o port (portc.1) as well as osci pin is used as the port c.0. free datasheet http:///
SH69P26 13 capacitor selection for oscillator ceramic resonators frequency c1 c2 recommend type manufacturer 455khz 47 - 100pf 47 - 100pf zt 455e jingbo electronic shenzhen 3.58mhz - - zt 3.58m* jingbo electronic shenzhen 4mhz - - zt 4m* jingbo electronic shenzhen *- the specified ceramic resonator has internal built-in load capacity crystal oscillator frequency c1 c2 recommend type manufacturer 32.768khz 5 - 12.5pf 5 - 12.5pf dt 38 ( 3 x 8) kds 4mhz 8 - 15pf 8 - 15pf 49s-4.000m-f16e jingbo electronic shenzhen 8mhz 8 - 15pf 8 - 15pf 49s-8.000m-f16e jingbo electronic shenzhen notes: 1. capacitor values are used for design guidance only! 2. these capacitors were tested with the crystal s listed above for basic start-up and operation. they are not optimized. 3. be careful for the stray capacitance on pcb board, the user should test the performance of the oscillator over the expected v dd and the temperature range for the application. before selecting crystal/ceramic, the user should consult the crystal/ceramic manufac turer for appropriate value of external component to get best performance, visit http://www.sinowealth.com for more recommended manufactures free datasheet http:///
SH69P26 14 6. i/o ports the mcu provides 29 bi-directional i/o ports. the port data put in register $08 - $0d, $22 - $23. the port control register ($16 - $21) controls the port as input or output. each i/o port has an internal pull-high resistor, which is controlled by the value of the corresponding bit in the pull-high control register ($24 - $2b), independently. when the port is selected as an input port, write ?1? to the re levant bit in the port pull-high control register ($24 - $2b) co uld turn on the pull-high resistor and write ?0? could turn off the pull-high resistor. when the port is selected as output port, the pull-high resistor will be turned off automatically, regardless the value of the corresponding bit in the port pull-high control register ($24 - $2b). when portf is selected as the digital input direction, they can active port interrupt by falling edge (if port interrupt is ena bled). system register $08 - $0d, $22 - $23: port data register address bit3 bit2 bit1 bit0 r/w remarks $08 pa.3 pa.2 pa.1 pa.0 r/w porta $09 pb.3 pb.2 pb.1 pb.0 r/w portb $0a pc.3 pc.2 pc.1 pc.0 r/w portc $0b pd.3 pd.2 pd.1 pd.0 r/w portd $0c pe.3 pe.2 pe.1 pe.0 r/w porte $0d pf.3 pf.2 pf.1 pf.0 r/w portf $22 pg.3 pg.2 pg.1 pg.0 r/w portg $23 - - ph.1 ph.0 r/w porth note: in 28 pin mode, all bits of the $22 ram are reserv ed, always keep it to ?0? in the user?s program. system register port $16 - $1b, $20 - $21: port control register address bit3 bit2 bit1 bit0 r/w remarks $16 pacr.3 pacr.2 pacr.1 pacr.0 r /w porta input/output control $17 pbcr.3 pbcr.2 pbcr.1 pbcr.0 r /w portb input/output control $18 pccr.3 pccr.2 pccr.1 pccr.0 r/w portc input/output control $19 pdcr.3 pdcr.2 pdcr.1 pdcr.0 r/w portd input/output control $1a pecr.3 pecr.2 pecr.1 pecr.0 r /w porte input/output control $1b pfcr.3 pfcr.2 pfcr.1 pfcr.0 r/w portf input/output control $20 pgcr.3 pgcr.2 pgcr.1 pgcr.0 r /w portg input/output control $21 - - phcr.1 phcr.0 r/w porth input/output control note: in 28 pin mode, all bits of the $20 ram are reserv ed, always keep it to ?1? in the user?s program. pa (/b/c/d/e/f/g/h) cr.n, (n = 0, 1, 2, 3) 0: set i/o as an input dire ction. (power on initial) 1: set i/o as an output direction. system register $24 - $2b: port pull-high control register address bit3 bit2 bit1 bit0 r/w remarks $24 ppacr.3 ppacr.2 ppacr.1 pp acr.0 r/w porta pull-high control $25 ppbcr.3 ppbcr.2 ppbcr.1 pp bcr.0 r/w portb pull-high control $26 - ppccr.2 ppccr.1 ppccr.0 r/w portc pull-high control $27 ppdcr.3 ppdcr.2 ppdcr.1 ppdcr.0 r/w portd pull-high control $28 ppecr.3 ppecr.2 ppecr.1 pp ecr.0 r/w porte pull-high control $29 ppfcr.3 ppfcr.2 ppfcr.1 ppf cr.0 r/w portf pull-high control $2a ppgcr.3 ppgcr.2 ppgcr.1 ppgcr.0 r/w portg pull-high control $2b - - pphcr.1 pphcr.0 r/w porth pull-high control ppa (/b/c/d/e/f/g/h) cr.n, (n = 0, 1, 2, 3) 0: disable internal pull-high resistor. (power on initial) 1: enable internal pull-high resistor. free datasheet http:///
SH69P26 15 equivalent circuit for a single i/o pin i/o control register data register pull high register m2t1 0 1 s read data in data read i/o pin pull high v dd gnd v dd in SH69P26, each output port contains a latch, which can hold the output data. writing the port data register (pdr) under the output mode can directly transfer da ta to the corresponding pad. all input ports do not have latches, so the external input data should be held externally until the input data is read from out side or reading the port data register (pdr) under the input mode when a digital i/o port is selected to be an output, the read ing of the associated port bit actually represents the value of th e output data latch, not the voltage on the pad. when a digital i/o port is selected to be an input, the re ading of the associated port bit represents the status on the corresponding pad. porta, portb, portd and porth have powe rful drive ability, and they can drive led numeric display directly. portb, portd [3:2], porth can source 25ma current. porta, portd [1:0] can sink 200ma current. for detail information, please reference the application circuit. - portc.2 can be shared with t0 input, - porte.0 can be shared with comparator output, - porte.1 can be shared with comparator negative input, - porte.2 can be shared with comparator positive input1, - porte.3 can be shared with comparator positive input2, - portf.0 can be shared with tone output, - portf.1 can be shared with t2 input, - portg.0 can be shared with comparator positive input6, - portg.1 can be shared with comparator positive input5, - portg.2 can be shared with comparator positive input4, - portg.3 can be shared with comparator positive input3, - the osci pin can be shared with portc.0, if the SH69P26 uses the internal rc oscillator as the system oscillation. - the osco pin can be shared with portc.1, if the SH69P26 uses the external clock or the rc oscillator as the system oscillatio n. - reset pin can be share as portc.3 (open drain). note: 1. porta, portd [1:0] can sink 200ma current. however only one port can be used to sink as large as 200ma current in the same time. 2. if external reset pin is enabled (portc.3 is shared as re set pin), SH69P26 will provide better performance on electro magnetic compatibility (emc). free datasheet http:///
SH69P26 16 port interrupt & cmp interrupt the portf are used as external port interrupt sources. sinc e portf are bit programmable i/os, only the voltage transition from v dd to gnd applying to the digital input port can generate a external interrupt. the analog input cannot generate any interrupt request. rising or falling on the comparat or output can also generate external interrupt. the interrupt control flags are mapped on $390, $392and $394 of the system register. they can be accessed or tested by the read or write operation. those flags are cleared to ?0? at the initialization by the chip reset. port interrupts (including comparator output interrupt) can be used to wake up the cpu from the halt or the stop mode. system register $390: port in terrupt enable flags register address bit 3 bit 2 bit 1 bit 0 r/w remarks $390 pfien.3 pfien.2 pfien.1 pfie n.0 r/w portf interrupt enable flags pfien.n, (n = 0, 1, 2, 3) 0: disable port interrupt. (power on initial) 1: enable port interrupt. system register $392: port interrupt request flags register address bit 3 bit 2 bit 1 bit 0 r/w remarks $392 pfif.3 pfif.2 pfif.1 pfif.0 r/w portf interrupt request flags pfif.n, (n = 0, 1, 2, 3) 0: port interrupt is not presented. (power on initial) 1: port interrupt is presented. only writing these bits to 0 is available. system register $394: comparator interrupt enable flags register address bit 3 bit 2 bit 1 bit 0 r/w remarks $394 - - cmpif cmpie r/w bit0: cmp output interrupt enable flag bit1: cmp output interrupt request flag cmpie 0: cmp output interrupt disable. (power on initial) 1: cmp output interrupt enable. cmpif 0: cmp output interrupt not pr esented (power on initial) 1: cmp output interrupt presented only writing these bits to 0 is available. following is the port interrupt function block-diagram for reference. pfif.n cmpif pfien.n cmpie port interrupt iep irqp cmpen cmp rising/falling edge detector portf.n falling edge detector pfcr.n note: n = 0, 1, 2, 3 programming note: when the port falling edge is active, any one of i/o input pin transitions from v dd to gnd would set pfif.x to ?1?. together, if the pfien.x = 1, the port would generate an interrupt request (irqp = 1). port interrupt can wake the cpu from halt or stop mode. free datasheet http:///
SH69P26 17 7. timer 7.1. timer0/timer1 the device has three timers: two 8-bit timers (timer0, timer1) and one 16-bit timer (timer2). the timer0/tiemr1 has the following features: - 8-bit up-counting timer/counter - automatic re-load counter. - 8-level prescaler. - interrupt on overflow from $ff to $00. the following is a simplified timer0/timer1 block diagram. prescaler system clock t osc sync 8-bit counter tm.2 tm.0 tm.1 eor t0e t0s t0 mux the timers provide the following functions: - programmable interval timer function. - read counter value. 7.1.1. timer0/timer1 configuration and operation both the timer0 and timer1 consist of an 8-bit write-only timer load register (tl0l, tl0h; tl1l, tl1h) and an 8-bit read-only timer counter. each of them has both low-order digits and high-order digits. writing data into the timer load register (t0l, t0h; t1l, t1h) can initialize the timer counter. the low-order digit should be written first, and then the high-order digit. the timer/counter is automatically loaded with the contents of the load register when the high-order digit is written or the counter counts overflow from $ff to $00. timer load register: the register h controls the physical read and write operations. please follow these steps: write operation: low nibble first high nibble to update the counter read operation: high nibble first low nibble followed. load reg. h 8-bit timer counter load reg. l latch reg. l 7.1.2. timer0/timer1 mode register the timer0/timer1 can be programmed in several different prescalers by setting timer mode register (tm0, tm1). the 8-bit counter prescaler overflows output pulses. the timer mode registers (tm0, tm1) are 3-bit registers used for the timer control as shown in table 1 and table 2. these mode regi sters select the input pulse sources into the timer. table 1 timer0 mode register ($02) t0m.2 t0m.1 t0m.0 prescaler divide ratio clock source 0 0 0 /2 11 system clock/t0 0 0 1 /2 9 system clock/t0 0 1 0 /2 7 system clock/t0 0 1 1 /2 5 system clock/t0 1 0 0 /2 3 system clock/t0 1 0 1 /2 2 system clock/t0 1 1 0 /2 1 system clock/t0 1 1 1 /2 0 system clock/t0 table 2 timer1 mode register ($03) t1m.2 t1m.1 t1m.0 prescaler divide ratio clock source 0 0 0 /2 11 system clock 0 0 1 /2 9 system clock 0 1 0 /2 7 system clock 0 1 1 /2 5 system clock 1 0 0 /2 3 system clock 1 0 1 /2 2 system clock 1 1 0 /2 1 system clock 1 1 1 /2 0 system clock free datasheet http:///
SH69P26 18 7.1.3. external clock/event t0 as timer0 source when external clock/event t0 input as timer0 source, it is synchronized with the cpu system clock (system clock/4). the external source must follow certain constraints. the system clo ck samples it in instruction frame cycle. therefore it is necess ary to be high (at least 2 t osc ) and low (at least 2 t osc ). when the prescaler ratio selects /2 0 , it is the same as the system clock input. the requirement is as follows t0h (t0 high time) 2 * t osc + ? t t0l (t0 low time) 2 * t osc + ? t ; ? t = 20ns when another prescaler ratio is selected, the tm0 is scaled by the asynchronous ripple counter and so the prescaler output is symmetrical. then: 2 t0 * n time low t0 time high t0 = = where: t0 = timer0 input period n = prescaler value (2 0 , 2 1 , 2 2 , 2 3 , 2 5 , 2 7 , 2 9 , 2 11 ) the requirement is: t t * 2 2 t0 * n osc ? + or n t * 2 t * 4 t0 osc ? + so, the limitation is applied for the t0 period time only. the pulse width is not limited by this equation. it is summarized as follows: n t * 2 t * 4 period timer0 t0 osc ? + = timer0 mode register: $02 address bit3 bit2 bit1 bit0 r/w remarks $02 t0s - - - r/w bit3: t0 signal source 0 x x x r/w shared with portc.2, timer0 source is system clock 1 x x x r/w shared with t0 input, ti mer0 source is t0 input clock timer0 mode register: $03 address bit3 bit2 bit1 bit0 r/w remarks $03 t0e - - - r/w bit3: t0 signal edge 0 x x x r/w falling edge active 1 x x x r/w rising edge active free datasheet http:///
SH69P26 19 7.2. timer2 timer2 is a 16-bit timer, and it has the following features: - 16-bit up-counting timer/counter. - automatic re-load counter. - 8-level prescaler. - interrupt on overflow from $ffff to $0000. the following is a simplified timer2 block diagram. prescaler system clock t osc sync 16-bit counter tsc.2 tsc.0 tsc.1 eor t2sc tm2s1 t2 mux tm2s0 cmpout t2e the timer2 provides the following functions: - programmable interval timer function. - read counter value. 7.2.1. timer2 configuration and operation timer2 consists of a 16-bit write-only timer load register (t2dl, t2dml, t2dmh, t2dh) and a 16-bit read-only timer counter. each of them has low-order digits and high-order digits. writing data into th e timer load regi ster (t2dl, t2dml, t2dmh, t2dh) can in itialize the timer counter. the low-order digit should be written first, and then the high-order digit. the timer counter is automatically loaded with the contents of the load register when the high order digit is written or the counter counts overflow from $ffff to $0000. timer load register: since t he register h controls the physical read and write operations. please follow these steps: write operation: low nibble first high nibble to update the counter read operation: high nibble first low nibble followed. load reg. h 16-bit timer counter load reg. l latch reg. l latch reg. h 7.2.2. timer2 control register the timer2 can be programmed in several different modes: timer, external event counter, external trigger timer and pulse width measurement. timer2 control register: $15 address bit3 bit2 bit1 bit0 r/w remarks $15 t2go dec tm2s1 tm2s0 r/w bit1-0: timer2 mode select bit2: select directive edge active enable bit3: set timer2 function start x x 0 0 r/w timer with internal system clock x x 0 1 r/w event counter with external signal source x x 1 0 r/w timer with external trigger x x 1 1 r/w pulse width measurement 0 x x x r/w timer/counter stops (read: status; write: command) (default) 1 x x x r/w timer/counter starts (read: status; write: command) 7.2.3. timer2 external signal so urce (ess) select register t2 pin input and comparator output (cmpout) can be selected as timer2 external signal source (ess). if t2 pin input is selected as timer2 external signal source, portf.1 is shared as t2 pin. otherwise, portf.1 is shared as i/o. timer2 external signal source can be selected from cmpout, while porte.0 is shared as cmpout. timer2 external signal source select register: $1c address bit 3 bit 2 bit 1 bit 0 r/w remarks $1c - t2e t2sc - r/w bit1: select external signal source for timer2 bit2: timer2 external signal source edge bit3: low voltage reset flag (read and write 0 only) x x 0 x r/w external signal source (ess) is from t2, if t2sc = 0. portf.1 is shared as t2 x x 1 x r/w external signal source (ess) is from cmpout, if t2sc = 1. portf.1 is shared as i/o. x 0 x x r/w falling edge is active, if exte rnal signal source is selected for timer2 x 1 x x r/w rising edge is active, if exte rnal signal source is selected for timer2 free datasheet http:///
SH69P26 20 7.2.4. timer mode in this mode, timer2 is performed using the internal clock. t he contents of the timer2 counter register ($384 - $387) are loade d into the up-counter while the highest nibble ($387) has been writte n. the up-counter will start counting if the t2go (bit3) in the timer2 control register ($15) is set to 1. the timer2 interrupt will issue when the up-counter ov erflows from $ffff to $0000 if the interrupt enable register ($00) bit1 (iet2) is set to ?1?. after the t2go (bit3) in the timer2 control register ($15) has been set to ?1?, writing the timer2 counter register ($384 - $38 7) cannot affect the up-counter operating anymore. only when the t2go (bit3) in the timer2 control register ($15) has been reset to 0, the revised contents of the timer2 counter register ($384 - $387) will be loaded into the up-counter while the highest ni bble ($387) is written. timer2 prescaler register: $38e address bit 3 bit 2 bit 1 bit 0 r/w remarks $38e - t2sc.2 t2sc.1 t2sc.0 r/w bit 2-0: timer2 prescaler register x 0 0 0 r/w timer clock: system clock/2 11 x 0 0 1 r/w timer clock: system clock/2 9 x 0 1 0 r/w timer clock: system clock/2 7 x 0 1 1 r/w timer clock: system clock/2 5 x 1 0 0 r/w timer clock: system clock/2 3 x 1 0 1 r/w timer clock: system clock/2 2 x 1 1 0 r/w timer clock: system clock/2 1 x 1 1 1 r/w timer clock: system clock/2 0 7.2.5. external event counter mode in this mode, timer2 is performed using the external signal s ource (ess), which is selected by t2s and t2sc in the timer2 external signal source select register ($1c). the external ev ents are counted at the edge of ess. either the rising or falling edge can be selected with the external trigger controlled by the st atus of the t2e (bit2) in the timer2 external signal source select register ($1c). the contents of the timer2 counter regist er ($384 - $387) are loaded into the up-counter while the highe st nibble ($387) has been written. the up-counter will start counting if the t2go (bit3) in the timer2 control register ($15) is s et to 1. the timer2 interrupt will issue when the up-counter overflows from $ffff to $0000, if the interrupt enable register ($00) bi t1 (iet2) is set to ?1?. after the t2go (bit3) in the timer2 control register ($15) has been set to ?1?, writing the timer2 counter register ($384 - $38 7) cannot affect the up-counter operating anymore. only when the t2go (bit3) in the timer2 control register ($15) has been reset to 0, the revised contents of the timer2 counter register ($384 - $387) will be loaded into the up-counter while the highest ni bble ($387) is written. the external clock source must follow certain constraints. the sy stem clock samples it in instru ction frame cycle. therefore it is necessary to be high (at least 2 t osc ) and low (at least 2 t osc ). in this mode, the prescaler circuit will not affect the external clock input. that means the input clock will bypass the prescaler circuit, regardless the real value written by programming. so, the limitation is applied for the external clock period (t e ) time described as follows: t e (period time) 4 * t osc + 2 * ? t ; ? t = 20ns free datasheet http:///
SH69P26 21 7.2.6. external trigger timer mode in this mode, the counting is triggered by an external signal. this trigger is the edge of the ess input. either the rising or falling edge can be selected with the external trigger controlled by the st atus of the t2e (bit2) in the timer2 external signal source select register ($1c). but the source clock of the up-counter is an internal clock. the contents of the timer2 counter registe r ($384 - $387) are loaded into the up-counter while the highest nibble ($387) has been written. only after the t2go (bit3) in th e timer2 control register ($15) has been set to 1, a proper edge signal on the ess input can start counting. the timer2 interrupt will issue when the up-counter overflows from $ffff to $0000 if the interrupt enable register ($00) bit1 (iet2) is set to ?1?. when the timer2 interrupt is generated the up-counter is halted . the up-counter is restarted by the next selected edge of the ess input. when dec (bit2) in the timer2 control register ($15) is 1, inputting the edge to the reverse direction of the trigger edge sele cted by the former programming to start counti ng stops the operating and then re-load contents from the timer2 counter register ($384 - $387). inputting a proper constant pulse width can generat e interrupts. when dec (bit2) in the timer2 control register ($15) is 0, the reverse directive edge input is ignored. the ess input another active edge befo re the up-counter overflowing is also ignored. after the t2go (bit3) in the timer2 control register ($15) has been set to ?1?, writing the timer2 counter register ($384 - $38 7) can not affect the up-counter operating anymore. only when the t2go (bit3) in the timer2 control register ($15) has been reset to 0, the revised contents of the timer2 counter register ($384 - $387) will be loaded into the up-counter while the highest ni bble ($387) is written. the ess input signal must follow certain constraints. the system clock samples it in instruction frame cycle. therefore it is necessary to be high (at least 1/2 t timer clock ) and low (at least 1/2 t timer clock ). in this mode, the real value of the timer clock is selected by the state in the timer2 prescaler register. so, the limitation is applied for the external clock period (t e ) time described as follows: t e (period time) 1 * t timer clock + 2 * ? t ; ? t = 20ns t e (period time) (m * t osc ) + 2 * ? t where m = 2 3 , 2 4 , 2 5 , 2 6 , 2 8 , 2 10 , 2 12 or 2 14 timer2 control register: $15 (under the external trigger timer mode) address bit 3 bit 2 bit 1 bit 0 r/w remarks $15 t2go dec tm2s1 tm2s0 r/w bit1-0: timer2 mode select x 0 x x r/w bit2: reverse directive edge input is ignored x 1 x x r/w bit2: reverse directive edge input reloadsinternal up-counter timer2 prescaler register: $38e (under the external trigger timer mode and pulse width measurement mode) address bit 3 bit 2 bit 1 bit 0 r/w remarks $38e - t2sc.2 t2sc.1 t2sc.0 r/w bit2-0: timer2 prescaler register x 0 0 0 r/w timer clock: system clock/2 12 x 0 0 1 r/w timer clock: system clock/2 10 x 0 1 0 r/w timer clock: system clock/2 8 x 0 1 1 r/w timer clock: system clock/2 6 x 1 0 0 r/w timer clock: system clock/2 4 x 1 0 1 r/w timer clock: system clock/2 3 x 1 1 0 r/w timer clock: system clock/2 2 x 1 1 1 r/w timer clock: system clock/2 1 timer2 counter register: $384 - $387 address bit 3 bit 2 bit 1 bit 0 r/w remarks $384 t2d.3 t2d.2 t2d.1 t2d.0 r/w timer2 load/counter register low nibble $385 t2d.7 t2d.6 t2d.5 t2d.4 r/w timer2 load/counter register middle_l nibble $386 t2d.11 t2d.10 t2d.9 t2d.8 r/w timer 2 load/counter register middle_h nibble $387 t2d.15 t2d.14 t2d.13 t2d.12 r/w t imer2 load/counter register high nibble free datasheet http:///
SH69P26 22 ess internal clock ff9e ffff ff9c ff9d 00 ff9c ff9d ff9f ff9e up-counter t2go timer2 int trigger start (dec = 0) count start count start ess internal clock f062 m - 1 f060 f061 00 f061 f062 ffff f060 up-counter t2go timer2 int trigger start and stop (dec = 1) count start count start f060 m count relooad 7.2.7. pulse width measurement mode in this mode, timer2 is performed using a special function un der the timer mode in which counting is started on an edge of pulse waveform, which is from ess input. it is possible to measure the width of the pulse waveform by reading the up-counter values on state transitions of the pulse. the rising or falling edge of the pulse is selected by setting the t2e (bit2) in the timer2 external signal source select register ($1c). but the source clock of the up-counter is an internal clock selected by proper setting the t2sc (bit2-0) in the timer2 pr escaler register ($38e). when the t2go (bit 3) in the timer2 control register ($15) is set to ?1?, the contents of the up-counter must reset to ?0000h ?, automatically. then a rising (falling) edge signal of the pul se triggers the up-counter to start counting. at the next falling (rising) edge, the counter value is loaded to the timer2 counter register ($384 - $387), individual ly. simultaneously, the timer2 interrupt is ge nerated if the interrupt enable register ($00) bit1 (iet2) is set to 1. when dec (bit2) in the timer2 control register ($15) is 0, the timer2 is in the one-edge capture operation. if the rising edge is selected as the counter triggering signal, at the next falling edge , the timer2 interrupt request is generated. at the same tim e, the contents of the up-counter must be loaded to the timer2 c ounter register ($384 - $387) at first, then will be cleared again and the counter is halted. when the next rising edge applies, the up-counter starts counting for another measurement cycle. when dec (bit2) in the timer2 control register ($15) is 1, t he timer2 is in the double-edge capture operation. if the rising ed ge is selected as the counter triggering signal, at the next falling edge, the timer2 interrupt request is generated. at the same time, the contents of the up-counter must be loaded to the timer2 counte r register ($384 - $387) at firs t, then the counter continues counting. when the next rising edge applies, the timer2 interrupt request is also generated. at this time, the contents of the up-counter must be loaded to the timer2 counter register ($38 4 - $387) again, then the counter must be cleared and can be continued to start counting following measurement cycles. free datasheet http:///
SH69P26 23 in this mode, writing the timer2 counter register ($384 - $387) at any time cannot affect the up-counter operating anymore. in this mode, the pulse signal must follow certain constraints as in the external trigger timer mode. so, the limitation is app lied for the external clock period (te) time described as follows: t e (period time) 1 * t timer clock + 2 * ? t ; ? t = 20ns t e (period time) (m * t osc ) + 2 * ? t where m (prescaler value for timer2 internal clock) = 2 3 , 2 4 , 2 5 , 2 6 , 2 8 , 2 10 , 2 12 or 2 14 but, in order to correctly get the pulse measurement value in programming, a sufficient wait period must be needed for the relevant timer2 interrupt subroutine program. so, if dec (bit2) in the timer2 control r egister ($15) is 0, the timer2 is in the one-edge capture operation. the limitation is applied for the external clock period (te) time described as follows: t e (period time) 14 * t tsystem clock t e (period time) 14 * 4 * t osc the maximum value of these two equations shown above is valid to the proper application. if dec (bit2) in the timer2 control register ($15) is 1, the ti mer2 is in the double-edge captur e operation. the limitation is applied for the ess input signal high or low level period described as follows: t e (high or low level period time) 14 * t tsystem clock t e (high or low level period time) 14 * 4 * t osc ess internal clock 0002 0000 0001 n m 0002 n - 1 0000 up-counter t2go timer2 int one edge capture (dec = 0) count start count start 0000 m ess counter reg. xxxx 0001 n capture capture ess internal clock 0002 0000 0001 t m 0001 t - 1 t + 1 up-counter t2go timer2 int double edge capture (dec = 1) count start count start m+1 m ess counter reg. xxxx n t capture capture 0 n capture timer2 control register: $15 (under the pulse width measurement mode) address bit 3 bit 2 bit 1 bit 0 r/w remarks $15 t2go dec tm2s1 tm2s0 r/w bit1-0: timer2 mode select x 0 x x r/w bit2: one edge capture x 1 x x r/w bit2: double edge capture free datasheet http:///
SH69P26 24 8.interrupt four interrupt sources are available on SH69P26: - timer0 interrupt - timer1 interrupt - timer2 interrupt - external interrupts (including portf interrupts, comparator interrupt) interrupt control bits and interrupt service the interrupt control flags are mapped on $00 and $01 of the system register. they can be accesse d or tested by the program. those flags are cleared to ?0? at initialization by the chip reset. system register: address bit 3 bit 2 bit 1 bit 0 r/w remarks $00 iet0 iet1 iet2 iep r/w interrupt enable flags $01 irqt0 irqt1 irqt2 irqp r/w interrupt request flags when iex is set to ?1? and the interrupt request is generated (i rqx is 1), the interrupt will be activated and the vector addre ss will be generated from the priority pla corresponding to the interr upt sources. when an interrupt occurs, the pc and cy flag wi ll be saved into the stack memory and jump to the interrupt servic e vector address. after the interrupt occurs, all interrupt enab le flags (iex) are clear to ?0? automatically, so when irqx is 1 an d iex is set to ?1? again, the interrupt will be activated and the vector address will be generated from the priori ty pla corresponding to the interrupt sources. instruction execution n instruction execution i1 instruction execution i2 interrupt generated interrupt accepted vector generated stacking fetch vector address reset ie.x start at vector address inst.cycle 12345 interrupt servicing sequence diagram interrupt nesting: during the cpu interrupt service, the user can enable any inte rrupt enable flag before returning from the interrupt. the servic ing sequence diagram shows the next interrupt and the next nesting inte rrupt occurrences. if the interr upt request is ready and the instruction of execution n is ie enable, then the interrupt w ill start immediately after the next two instruction executions. however, if instruction i1 or instruction i2 disables the in terrupt request or enable flag, then the interrupt service will be terminated. timer (timer0, timer1, timer2) interrupt the input clock of timer0, timer1 and timer2 are based on syst em clocks or external clock/event t0 input as timer0 source and ess input as timer2 source. the timer overflow from $ff to $00 (from $ffff to $0000 for timer2) will generate an internal interrupt request (irqt0, irqt1 = 1 or irqt2 = 1), if the interru pt enable flag is enabled (iet0, iet1 = 1 or iet2 = 1), a time r interrupt service routine will start. timer interrupt can also be used to wake the cpu from the halt mode. external interrupt only the digital input port can generate an external interrupt. the analog input cannot generate an interrupt request. any one of the portf input pin transitions from v dd to gnd would generate an interrupt request (irqp = 1). rising or falling on the comparator outpu t can also generate external interrupt. port interrupt (including comparator output interrupt) ca n be used to wake the cpu from halt or stop mode. free datasheet http:///
SH69P26 25 port interrupts by bit only the digital input port can generate a port interrupt. the analog input cannot generate an interrupt request. system register: address bit 3 bit 2 bi t 1 bit 0 r/w remarks $390 pfien.3 pfien.2 pfien.1 pfien.0 r /w portf edge to interrupt enable $392 pfif.3 pfif.2 pfif.1 pfif.0 r/w portf edge detector flag system register: address bit 3 bit 2 bi t 1 bit 0 r/w remarks $394 - - cmpif cmpie r/w bit0: cmp output interrupt enable flag bit1: cmp output interrupt request flag application notice: when the port falling edge is active, any one of portf input pin transitions from v dd to gnd would set pfif.x to ?1?. together, if the pfien.x = 1, the port would generate an interrupt request (irqp = 1). port interrupt can wake the cpu from halt or stop mode. rising or falling on the comparator output would set cmpif to ?1?. toget her, if the cmpie = 1, the port would generate an interrupt request (irqp = 1). comparator interrupt can also wake the cpu from halt or stop mode. free datasheet http:///
SH69P26 26 9. analog comparator (cmp) comparator includes 1 negative input, 6 positive inputs and 1 ou tput. each of them can be selected individually by comparator control register (ccr). when cmpen is set to 1, the com parator enables. porte.1 input or internal reference voltage (v dd /2) can be selected as comparator negative input. one or more positive input should be selected. porte.0 can be shared as comparator output, if it is necessary. the rising or fa lling edge (selected by cmpe) will generate a cmp interrupt. system register $13: analog comparator control register (cmpc) address bit 3 bit 2 bit 1 bit 0 r/w remarks $13 cmpe cmpso cmpsn cmpen r/w comparator control register x x x 1 r/w comparator enable x x x 0 r/w comparator disable x x 1 x r/w porte.1 input is selected as comparator negative input x x 0 x r/w internal reference voltage (v dd /2) is selected as comparator negative input x 1 x x r/w porte.0 is shared as cmpout x 0 x x r/w porte.0 is shared as i/o 1 x x x r/w comparator output rising edge generate interrupt 0 x x x r/w comparator output falling edge generate interrupt comparator data register: ($38f) address bit 3 bit 2 bit 1 bit 0 r/w remarks $38f - cnf2 - cnf1 - cnf0 cmpod - r r/w cmpod: comparator output data cnf2-0: select comparator input channel at any time, if comparator is operati ng, cmpod equals the comparator output. comparator data register: ($38f) cnf2 cnf1 cnf0 5 4 3 2 1 0 0 0 0 portg.0 portg.1 portg.2 portg.3 porte.3 porte.2 0 0 1 portg.0 portg.1 portg.2 portg.3 porte.3 cmpp1 0 1 0 portg.0 portg.1 portg.2 portg.3 cmpp2 cmpp1 0 1 1 portg.0 portg.1 portg.2 cmpp3 cmpp2 cmpp1 1 0 0 portg.0 portg.1 cmpp4 cmpp3 cmpp2 cmpp1 1 0 1 portg.0 cmpp5 cmpp4 cmpp3 cmpp2 cmpp1 1 1 0 cmpp6 cmpp5 cmpp4 cmpp3 cmpp2 cmpp1 1 1 1 cmpp6 cmpp5 cmpp4 cmpp3 cmpp2 cmpp1 comparator status register ($14) address bit 3 bit 2 bit 1 bit 0 r/w remarks $14 cmpgo cmpsp2 cmpsp1 cmpsp0 r/w c omparator status register x 0 0 0 r/w comparator posit ive input is from cmpp1 x 0 0 1 r/w comparator posit ive input is from cmpp2 x 0 1 0 r/w comparator posit ive input is from cmpp3 x 0 1 1 r/w comparator posit ive input is from cmpp4 x 1 0 0 r/w comparator posit ive input is from cmpp5 x 1 0 1 r/w comparator posit ive input is from cmpp6 x 1 1 0 r/w comparator posit ive input is from cmpp6 x 1 1 1 r/w comparator posit ive input is from cmpp6 1 x x x r/w comparator output is valid 0 x x x r/w comparator output is invalid, and the output always equal zero note: 1. before enable the comparator, these registers must be set co rrectly. forbid connecting analog signal to any digital i/o. 2. when set cmpen to 1, system will take 3us to setup the comparator, including internal v dd /2. so wait 5us before set cmpgo to 1 3. when set cmpgo to 1, positive input or negative input channel cannot be changed. if it is necessary to change positive input or negative channel, clear cmpgo bit, when th e change is finished, set cmpgo to 1 again. free datasheet http:///
SH69P26 27 10. dual tone two channel tone is provided. they are the 12-bit pseudo rand om counter. to reduce power consumption, disable the sound effect generator during both stop and halt statuses. tone generator control register address bit 3 bit 2 bit 1 bit 0 r/w remarks $388 tg1.3 tg1.2 tg1.1 tg1.0 r/w tone generator 1 low nibble $389 tg1.7 tg1.6 tg1.5 tg1.4 r/w tone generator 1 middle nibble $38a tg1.11 tg1.10 tg1.9 tg1.8 r/w tone generator 1 high nibble $38b tg2.3 tg2.2 tg2.1 tg2.0 r/w tone generator 2 low nibble $38c tg2.7 tg2.6 tg2.5 tg2.4 r/w tone generator 2 middle nibble $38d tg2.11 tg2.10 tg2.9 tg2.8 r/w tone generator 2 high nibble tone generator volume control register address bit 3 bit 2 bit 1 bit 0 r/w remarks $2c tv1.3 tv1.2 tv1.1 tv1.0 r/w tone generator 1 volume low nibble $2d tg1en tv1.6 tv1.5 tv1.4 r/w tone generator 1 volume high nibble tg1en: tone generator 1 enable $2e tv2.3 tv2.2 tv2.1 tv2.0 r/w tone generator 2 volume low nibble $2f tg2en tv2.6 tv2.5 tv2.4 r/w tone generator 2 volume high nibble tg2en: tone generator 2 enable the volume control register has 7 bits used to control the output level of the tone generator. tgxen: tone generator x enable 0: tone generator x disable (power on initial) 1: tone generator x enable note: x = 1 or 2 programming notice: never execute the "halt" or "stop" instruction while the tone generator is playing. free datasheet http:///
SH69P26 28 music table 1. following is the music scale reference table for the tone generator channel 1(or channel 2) under osc = 4mhz. note ideal freq. n tgcr (tgx.11 - tgx.0) (x = 1 or 2) real freq. error% note ideal freq. n tgcr (tgx.11 - tgx.0) (x = 1 or 2) real freq. error% b2 123.47 4050 02e 123.46 -0.01 #f5 739.99 676 d5c 739.64 -0.05 c3 130.81 3822 112 130.82 0.01 g5 783.99 638 d82 783.70 -0.04 #c3 138.59 3608 1e8 138.58 -0.01 #g5 830.61 602 da6 830.56 -0.01 d3 146.83 3405 2b3 146.84 0.01 a5 880.00 568 dc8 880.28 0.03 #d3 155.56 3214 372 155.57 0.00 #a5 932.33 536 de8 932.84 0.06 e3 164.81 3034 426 164.80 -0.01 b5 987.77 506 e06 988.14 0.04 f3 174.61 2863 4d1 174.64 0.02 c6 1046.5 478 e22 1046.0 -0.05 #f3 185.00 2703 571 184.98 -0.01 #c6 1108.7 451 e3d 1108.7 -0.01 g3 196.00 2551 609 196.00 0.00 d6 1174.7 426 e56 1173.7 -0.08 #g3 207.65 2408 698 207.64 -0.01 #d6 1244.5 402 e6e 1243.8 -0.06 a3 220.00 2273 71f 219.97 -0.01 e6 1318.5 379 e85 1319.3 0.06 #a3 233.08 2145 79f 233.10 0.01 f6 1396.9 358 e9a 1396.7 -0.02 b3 246.94 2025 817 246.91 -0.01 #f6 1480.0 338 eae 1479.3 -0.05 c4 261.63 1911 889 261.64 0.01 g6 1568.0 319 ec1 1567.4 -0.04 #c4 277.18 1804 8f4 277.16 -0.01 #g6 1661.2 301 ed3 1661.1 -0.01 d4 293.66 1703 959 293.60 -0.02 a6 1760.0 284 ee4 1760.6 0.03 #d4 311.13 1607 9b9 311.14 0.00 #a6 1864.7 268 ef4 1865.7 0.05 e4 329.63 1517 a13 329.60 -0.01 b6 1975.5 253 f03 1976.3 0.04 f4 349.23 1432 a68 349.16 -0.02 c7 2093.0 239 f11 2092.1 -0.05 #f4 369.99 1351 ab9 370.10 0.03 #c7 2217.5 225 f1f 2222.2 0.22 g4 392.00 1276 b04 391.85 -0.04 d7 2349.3 213 f2b 2347.4 -0.08 #g4 415.30 1204 b4c 415.28 -0.01 #d7 2489.0 201 f37 2487.6 -0.06 a4 440.00 1136 b90 440.14 0.03 e7 2637.0 190 f42 2631.6 -0.21 #a4 466.16 1073 bcf 465.98 -0.04 f7 2793.8 179 f4d 2793.3 -0.02 b4 493.88 1012 c0c 494.07 0.04 #f7 2960.0 169 f57 2958.6 -0.05 c5 523.25 956 c44 523.01 -0.05 g7 3136.0 159 f61 3144.7 0.28 #c5 554.37 902 c7a 554.32 -0.01 #g7 3322.4 150 f6a 3333.3 0.33 d5 587.33 851 cad 587.54 0.04 a7 3520.0 142 f72 3521.1 0.03 #d5 622.25 804 cdc 621.89 -0.06 #a7 3729.3 134 f7a 3731.3 0.05 e5 659.26 758 d0a 659.63 0.06 b7 3951.1 127 f81 3937.0 -0.36 f5 698.46 716 d34 698.32 -0.02 c8 4186.0 119 f89 4201.7 0.37 free datasheet http:///
SH69P26 29 music table 2. following is the music scale reference table for the tone generator channel 1(or channel 2) under osc =2mhz. note ideal freq. n tgcr (tgx.11 - tgx.0) (x = 1 or 2) real freq. error% note ideal freq. n tgcr (tgx.11 - tgx.0) (x = 1 or 2) real freq. error% b1 61.73 4050 2e 61.73 0.00 c5 523.25 478 e22 523.01 -0.05 c2 65.10 3840 100 65.10 0.00 #c5 554.37 451 e3d 554.32 -0.01 #c2 69.29 3608 1e8 69.29 0.00 d5 587.33 426 e56 586.85 -0.08 d2 73.42 3405 2b3 73.42 0.00 #d5 622.25 402 e6e 621.89 -0.06 #d2 77.78 3214 372 77.78 0.00 e5 659.26 379 e85 659.63 0.06 e2 82.41 3034 426 82.40 -0.01 f5 698.46 358 e9a 698.32 -0.02 f2 87.31 2863 4d1 87.32 0.01 #f5 739.99 338 eae 739.64 -0.05 #f2 92.50 2703 571 92.49 -0.01 g5 783.99 319 ec1 783.70 -0.04 g2 98.00 2551 609 98.00 0.00 #g5 830.61 301 ed3 830.56 -0.01 #g2 103.82 2408 698 103.82 0.00 a5 880.00 284 ee4 880.28 0.03 a2 110.00 2273 71f 109.99 -0.01 #a5 932.33 268 ef4 932.84 0.06 #a2 116.54 2145 79f 116.55 0.01 b5 987.77 253 f03 988.14 0.04 b2 123.47 2025 817 123.46 -0.01 c6 1046.5 239 f11 1046.0 -0.05 c3 130.81 1911 889 130.82 0.01 #c6 1108.7 225 f1f 1111.1 0.22 #c3 138.59 1804 8f4 138.58 -0.01 d6 1174.7 213 f2b 1173.7 -0.08 d3 146.83 1703 959 146.80 -0.02 #d6 1244.5 201 f37 1243.8 -0.06 #d3 155.56 1607 9b9 155.57 0.00 e6 1318.5 190 f42 1315.8 -0.21 e3 164.81 1517 a13 164.80 -0.01 f6 1396.9 179 f4d 1396.7 -0.02 f3 174.61 1432 a68 174.58 -0.02 #f6 1480.0 169 f57 1479.3 -0.05 #f3 185.00 1351 ab9 185.05 0.03 g6 1568.0 159 f61 1572.3 0.28 g3 196.00 1276 b04 195.92 -0.04 #g6 1661.2 150 f6a 1666.7 0.33 #g3 207.65 1204 b4c 207.64 -0.01 a6 1760.0 142 f72 1760.6 0.03 a3 220.00 1136 b90 220.07 0.03 #a6 1864.7 134 f7a 1865.7 0.05 #a3 233.08 1073 bcf 232.99 -0.04 b6 1975.5 127 f81 1968.5 -0.36 b3 246.94 1012 c0c 247.04 0.04 c7 2093.0 119 f89 2100.8 0.37 c4 261.63 956 c44 261.51 -0.04 #c7 2217.5 113 f8f 2212.4 -0.23 #c4 277.18 902 c7a 277.16 -0.01 d7 2349.3 106 f96 2358.5 0.39 d4 293.66 851 cad 293.77 0.04 #d7 2489.0 100 f9c 2500.0 0.44 #d4 311.13 804 cdc 310.95 -0.06 e7 2637.0 95 fa1 2631.6 -0.21 e4 329.63 758 d0a 329.82 0.06 f7 2793.8 89 fa7 2809.0 0.54 f4 349.23 716 d34 349.16 -0.02 #f7 2960.0 84 fac 2976.2 0.55 #f4 369.99 676 d5c 369.82 -0.05 g7 3136.0 80 fb0 3125.0 -0.35 g4 392.00 638 d82 391.85 -0.04 #g7 3322.4 75 fb5 3333.3 0.33 #g4 415.30 602 da6 415.28 -0.01 a7 3520.0 71 fb9 3521.1 0.03 a4 440.00 568 dc8 440.14 0.03 #a7 3729.3 67 fbd 3731.3 0.05 #a4 466.16 536 de8 466.42 0.06 b7 3951.1 63 fc1 3968.3 0.44 b4 493.88 506 e06 494.07 0.04 c8 4186.0 60 fc4 4166.7 -0.46 free datasheet http:///
SH69P26 30 11. low voltage reset (lvr) the lvr function is to monitor the supply voltage and generate an internal reset in the device. it is typically used in ac line applications or large battery where large loads may be switched in and cause the device voltage to temporarily fall below the specified operating minimum. the lvr function is selected by code option. the lvr circuit has the following functions when lvr function is enabled: - generates a system reset when v dd v lvr . - cancels the system reset when v dd > v lvr . 12. watchdog timer (wdt) the watchdog timer is a count-down counter, and its clock sour ce is an independent built-in rc oscillator, so that it will alwa ys run even in the stop mode. the watchdog timer automatically generates a device reset when it overflows. it can be enabled or disabled permanently by using the code option. the watchdog timer control bits ($1e bit2 - bit0) are used to se lect different overflow frequenc y. the watchdog timer overflow flag ($1e bit3) will be automatically set to ?1? by hardware when the watchdog timer overflows. by reading or writing the syste m register $1e, the watchdog timer should re-count before the overflow happens. system register $1e: watchdog timer (wdt) address bit 3 bit 2 bit 1 bit 0 r/w remarks $1e - wdt wdt.2 - wdt.1 - wdt.0 - r/w r bit2-0: watchdog timer control bit3: watchdog timer overflow flag (read only) x 0 0 0 r/w watchdog timer-out period = 4096ms x 0 0 1 r/w watchdog timer-out period = 1024ms x 0 1 0 r/w watchdog timer-out period = 256ms x 0 1 1 r/w watchdog timer-out period = 128ms x 1 0 0 r/w watchdog timer-out period = 64ms x 1 0 1 r/w watchdog timer-out period = 16ms x 1 1 0 r/w watchdog timer-out period = 4ms x 1 1 1 r/w watchdog timer-out period = 1ms 0 x x x r no watchdog timer overflow reset 1 x x x r watchdog timer overflow, wdt reset happens note: watchdog timer-out period valid for v dd = 5v. 13. halt and stop mode after the execution of halt instruction, SH69P26 will enter th e halt mode. in the halt mode, cpu will stop operating. but peripheral circuit (timer0, timer1, timer2, cmp and watchdog timer) will keep status. after the execution of stop instruction, SH69P26 will enter th e stop mode. the whole chip (inc luding oscillator) will stop operating. but watchdog and cmp are still enabled. in the halt mode, SH69P26 can be waked up if any interrupt occurs. in the stop mode, SH69P26 can be waked up if any port interr upt (including other external sources, such as cmp output interrupt) occurs or watchdog timer overflows (wdt is enabled). 14. warm-up timer the device has a built-in warm-up timer to eliminate unstable stat e of initial oscillation when o scillator starts oscillating i n the following conditions: power-on reset, pin reset: warm-up time interval: (1) in rc oscillator mode, f osc = 32.768khz - 6mhz, the warm-up counter prescaler divide ratio is 2 12 (4096). (2) in crystal oscillator or ceramic resonator mode, f osc = 32.768khz - 8mhz, the warm-up c ounter prescaler divide ratio is 2 14 (16384). wake up from stop mode, wdt reset & lvr reset: warm-up time interval: (1) in rc oscillator mode, f osc = 32.768khz - 6mhz, the warm-up counter prescaler is divided by 2 7 (128). (2) in crystal oscillator or ceramic resonator mode, f osc = 32.768khz - 8mhz, the warm-up counter prescaler is divided by 2 12 (4096). free datasheet http:///
SH69P26 31 15. code option osc: 000: external clock (default) 001: internal rc oscillator (2mhz) 010: internal rc oscillator (4mhz) 011: internal rc oscillator (6mhz) 100: external rc oscillator (400khz - 8mhz) 101: ceramic resonator (400khz - 8mhz) 110: crystal oscillator (400khz - 8mhz) 111: 32.768khz crystal oscillator osc range: 0: 2mhz - 8mhz (default) 1: 400khz - 2mhz wdt: 0: enable (default) 1: disable lvr: 0: disable (default) 1: enable lvr voltage range: 0: high lvr voltage (default) 1: low lvr voltage chip pin reset*: 0 = pin reset function is enabled (default) 1 = pin reset function is disabled * note: 1. reset pin can be shared as io. 2. if reset pin is enabled, the emc quality will be better. free datasheet http:///
SH69P26 32 in system programming notice for otp the in system programming technology is valid for otp chip. the programming interface of the otp chip must be set on user?s application pcb, and users can assemble all components including the otp chip in the application pcb before programmi ng the otp chip. of course, it?s accessible bonding otp chip only first, and then programming code and finally assembling other components. since the programming timing of progr amming interface is very sensitiv e, therefore four jumpers are needed (v dd , v pp , sda, sck) to separate the programming pins from the appl ication circuit as shown in the following diagram. otp chip v pp v dd sck sda gnd to application circuit jumper application pcb otp writer the recommended steps are the followings: (1) the jumpers are open to separate the programming pins from the application circuit before programming the chip. (2) connect the programming interface wi th otp writer and begin programming. (3) disconnect otp writer and shorten these jumpers when programming is completed. for more detail information, please refer to the otp writer user manual. free datasheet http:///
SH69P26 33 instruction set all instructions are one cycle and one-word instructio ns. the characteristic is memory-oriented operation. 1. arithmetic and logical instruction 1.1 accumulator type mnemonic instruction code function flag change adc x (, b) 00000 0bbb xxx xxxx ac <- mx + ac + cy cy adcm x (, b) 00000 1bbb xxx x xxx ac, mx <- mx + ac + cy cy add x (, b) 00001 0bbb xxx xxxx ac <- mx + ac cy addm x (, b) 00001 1bbb xxx xxxx ac, mx <- mx + ac cy sbc x (, b) 00010 0bbb xxx xxxx ac <- mx + -ac + cy cy sbcm x (, b) 00010 1bbb xxx x xxx ac, mx <- mx + -ac + cy cy sub x (, b) 00011 0bbb xxx xxxx ac <- mx + -ac +1 cy subm x (, b) 00011 1bbb xxx x xxx ac, mx <- mx + -ac +1 cy eor x (, b) 00100 0bbb xxx xxxx ac <- mx ac eorm x (, b) 00100 1bbb xxx xxxx ac, mx <- mx ac or x (, b) 00101 0bbb xxx xxxx ac <- mx | ac orm x (, b) 00101 1bbb xxx xxxx ac, mx <- mx | ac and x (, b) 00110 0bbb xxx xxxx ac <- mx & ac andm x (, b) 00110 1bbb xxx xxxx ac, mx <- mx & ac shr 11110 0000 000 0000 0 -> ac[3], ac[0] -> cy; ac shift right one bit cy 1.2. immediate type mnemonic instruction code function flag change adi x, i 01000 iiii xxx xxxx ac <- mx + i cy adim x, i 01001 iiii xxx xxxx ac, mx <- mx + i cy sbi x, i 01010 iiii xxx xxxx ac <- mx + -i +1 cy sbim x, i 01011 iiii xxx xxxx ac, mx <- mx + -i +1 cy eorim x, i 01100 iiii xxx xxxx ac, mx <- mx i orim x, i 01101 iiii xxx xxxx ac, mx <- mx | i andim x, i 01110 iiii xxx xxxx ac, mx <- mx & i 1.3. decimal adjustment mnemonic instruction code function flag change daa x 11001 0110 xxx xxxx ac, mx <- decimal adjust for add cy das x 11001 1010 xxx xxxx ac, mx <- decimal adjust for sub cy free datasheet http:///
SH69P26 34 2. transfer instruction mnemonic instruction code function flag change lda x (, b) 00111 0bbb xxx xxxx ac <- mx sta x (, b) 00111 1bbb xxx xxxx mx <- ac ldi x, i 01111 iiii xxx xxxx ac, mx <- i 3. control instruction mnemonic instruction code function flag change baz x 10010 xxxx xxx xxxx pc <- x, if ac = 0 bnz x 10000 xxxx xxx xxxx pc <- x, if ac 0 bc x 10011 xxxx xxx xxxx pc <- x, if cy = 1 bnc x 10001 xxxx xxx xxxx pc <- x, if cy 1 ba0 x 10100 xxxx xxx xxxx pc <- x, if ac (0) = 1 ba1 x 10101 xxxx xxx xxxx pc <- x, if ac (1) = 1 ba2 x 10110 xxxx xxx xxxx pc <- x, if ac (2) = 1 ba3 x 10111 xxxx xxx xxxx pc <- x, if ac (3) = 1 call x 11000 xxxx xxx xxxx st <- cy, pc +1 pc <- x (not include p) rtnw h, l 11010 000h hhh llll pc <- st; tbr <- hhhh, ac <- lll rtni 11010 1000 000 0000 cy, pc <- st cy halt 11011 0000 000 0000 stop 11011 1000 000 0000 jmp x 1110p xxxx xxx xxxx pc <- x (include p) tjmp 11110 1111 111 1111 pc <- (pc11-pc8) (tbr) (ac) nop 11111 1111 111 1111 no operation where, pc program counter i immediate data ac accumulator logical exclusive or -ac complement of accumulator | logical or cy carry flag & logical and mx data memory bbb ram bank p rom page st stack tbr table branch register free datasheet http:///
SH69P26 35 electrical characteristics absolute maximum ratings* dc supply voltage . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v input voltage . . . . . . . . . . . . . . . . . . . .-0.3v to v dd + 0.3v operating ambient temperature . . . . . . .. . -40c to +85c storage temperature . . . . . . . ? . . . . . . . -55c to +125c *comments stresses exceed those listed under ?absolute maximum ratings? may cause permanent damage to this device. these are stress ratings only. functional operation of this device under these or any other conditions exceed those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristic (gnd = 0v, t a = 25c, unless otherwise specified.) parameter symbol min. typ. max. unit condition 4.5 5.0 5.5 v f osc = 8mhz operating voltage v dd 2.4 5.0 5.5 v f osc = 4mhz low voltage reset voltage1 v lvr1 3.8 - 4.2 v lvr enable low voltage reset voltage2 v lvr2 2.3 - 2.7 v lvr enable lvr voltage pulse width t lvr 500 - - sv dd v lvr - 1.5 2 ma f osc = 8mhz all output pins unloaded, execute nop instruction, (wdt off, lvr off, cmp disable.) v dd = 5.0v operating current i op - 1.0 1.5 ma f osc = 4mhz all output pins unloaded, execute nop instruction, (wdt off, lvr off, cmp disable.) v dd = 5.0v stand by current 1 (halt) i sb1 - - 1 ma f osc = 8mhz, all output pins unloaded (halt mode), wdt off, lvr off, cmp disable, v dd = 5.0v stand by current 2 (halt) i sb2 - - 0.8 ma f osc = 4mhz, all output pins unloaded (halt mode), wdt off, lvr off, cmp disable, v dd = 5.0v stand by current 3 (stop) i sb3 - - 1 a all output pins unloaded (stop mode), wdt off, lvr off, cmp disable, v dd = 5.0v wdt current i wdt - - 20 a stop, wdt on, cmp disable, lvr off, v dd = 5.0v dc electrical characte ristics (continued1) (gnd = 0v, t a = 25 , f osc = 4mhz, unless otherwise specified) parameter symbol min. typ. max. unit condition input low voltage v il1 gnd - v dd x 0.2 v i/o ports, pins tri-state, v dd = 5.0v input low voltage v il2 gnd - v dd x 0.15 v reset , t0, t2, osci (schmitt trigger), v dd = 5.0v input high voltage v ih1 v dd x 0.8 - v dd v i/o ports, pins tri-state, v dd = 5.0v input high voltage v ih2 v dd x 0.85 - v dd v reset , t0, t2, osci (schmitt trigger), v dd = 5.0v input leakage current i il -1 - 1 a i/o ports, gnd < v in < v dd pull-high resistor r ph - 30 - k ? pull-high/pull-low resistor (v dd = 5.0v) output high voltage v oh1 v dd - 1.0 - - v i/o ports, i oh = -25ma (portb, porth, portd [3:2]) output high voltage v oh2 v dd - 0.7 - - v i/o ports, i oh = -10ma (porta, portc, portd [1:0], porte, portf, portg), v dd = 5.0v output low voltage v ol1 - - gnd + 1.5 v i/o ports, i ol = 200ma (porta, portd [1:0]), v dd = 5.0v output low voltage v ol2 - - gnd + 0.6 v i/o ports, i ol = 20ma (portb, porth, portd [3:2], portc, porte, portf, portg), v dd = 5.0v dc electrical characte ristics (continued2) (gnd = 0v, t a = 25 , f osc = 8mhz, unless otherwise specified) parameter symbol min. typ. max. unit condition input low voltage v il3 gnd - v dd x 0.2 v i/o ports, pins tri-state, v dd = 5.0v input high voltage v ih3 v dd x 0.8 - v dd v i/o ports, pins tri-state, v dd = 5.0v free datasheet http:///
SH69P26 36 ac electrical characteristics (v dd = 2.4v - 5.5v, gnd = 0v, t a = 25c, unless otherwise specified.) parameter symbol min. typ. max. unit condition instruction cycle time t cy 0.5 - 133.4 s f osc = 30khz - 8mhz t0/t2 input width t iw (t cy + 40)/n - - ns n = prescaler divide ratio, v dd = 5.0v input pulse width t ipw t iw /2 - - ns v dd = 5.0v reset pulse width t reset 10 - - s low active, v dd = 5.0v wdt period t wdt 1 - - ms v dd = 5.0v frequency variation |? f|/f - - 15 % external r osc oscillator, include chip-to-chip variation, v dd = 5v frequency variation |? f|/f - - 50 % internal r osc oscillator, f osc = 2mhz, 4mhz, 6mhz. include chip-to-chip variation, v dd = 5v analog comparator electrical characteristics (v dd = 4.5v - 5.5v, gnd = 0v, t a = -40c to +85c, f osc = 30khz - 10mhz, porte.1 input is selected as comparator negative input. unless otherwise specified.) parameter symbol min. typ. max. unit condition offset voltage comparator inputs | v io | - - 10 mv v dd = 5.0v common mode range comparator inputs v cm gnd - v dd - 1.0 v v dd = 5.0v response time t res - 250 500 ns v dd = 5.0v comparator enable to output valid time t ov - - 10 s v dd = 5.0v input leakage current i il - - 10 a 0 < v in < v dd free datasheet http:///
SH69P26 37 timing waveform (a) system clock timing waveform t1 t2 t3 t4 t5 t6 t7 t8 t1 t2 t3 t4 f osc system clock t cy (b) t0/t2 input waveform t iw t ipw(l) t ipw(h) t0/t2 input signal rc oscillator characteristics graphs (for reference only) typical rc oscillator resistor vs. frequency (v dd = 4.5 - 5.5v) typical rc oscillator re sistor vs. f requency (v dd = 5v) 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 0.00 50.00 100.00 150.00 200.00 250.00 typical rc oscillator resistor: r osc (k ? ) frequency: f osc (mhz) free datasheet http:///
SH69P26 38 application circuit (for reference only) ap: SH69P26 has powerful drive ability, and it can drive led directly. (1) operating voltage: 5.0v (2) oscillator: crystal resonator 4mhz (3) porta, b, d, h: output v dd osci /portc.0 osco /portc.1 v dd c1 0.1u r1 y1 cry c3 15p reset c4 15p c2 0.1u gnd portb.3 portb.1 portb.2 portb.0 portd.3 porth.1 portd.2 porth.0 porta.0 porta.2 porta.1 porta.3 portd.0 portd.1 tone cmpp1 cmpp2 comparator positive input2 comparator positive input1 r2 q1 r3 r4 r5 r6 r7 r8 r9 r10 SH69P26 47k v dd speaker 0.2k 0.2k 0.2k 0.2k 0.2k 0.2k 0.2k 0.2k 10k free datasheet http:///
SH69P26 39 ordering information part no. package SH69P26k 28l skinny SH69P26m 28l sop SH69P26 32l dip free datasheet http:///
SH69P26 40 package information skinny 28-pin outline dimensions unit: inches/mm 114 15 28 d e 1 base plane b 1 e 1 s a 2 a l a 1 mounting plane b c e e a symbol dimensions in inches dimensions in mm a 0.175 max. 4.45 max. a 1 0.010 min. 0.25 min. a 2 0.130 0.005 3.30 0.13 0.018+ 0.004 0.46+ 0.10 b - 0.002 - 0.05 0.060+ 0.004 1.52+ 0.10 b 1 - 0.002 - 0.05 0.010+0.004 0.25+ 0.10 c -0.002 - 0.05 d 1.388 typ. (1.400 max.) 35.26 typ. (35.56 max.) e 0.310 0.010 7.87 0.25 e 1 0.288 0.005 7.32 0.13 e 1 0.100 0.010 2.54 0.25 l 0.130 0.010 3.30 0.25 0 - 15 0 - 15 e a 0.350 0.020 8.89 0.51 s 0.055 max. 1.40 max. notes: 1. the maximum value of dimension d includes end flash. 2. dimension e 1 does not include resin fins. 3. dimension s includes end flash. free datasheet http:///
SH69P26 41 sop (n.b.) 28l outline dimensions unit: inches/mm 1 e h e l l e c 14 see detail f detail f b 15 28 e 1 e 1 a 1 a 2 a s d seating plane d y e ~ ~ ~ symbol dimensions in inches dimensions in mm a 0.110 max. 2.79 max. a 1 0.004 min. 0.10 min. a 2 0.093 0.005 2.36 0.13 0.016 +0.004 0.41 +0.10 b -0.002 -0.05 0.010 +0.004 0.25 +0.10 c -0.002 -0.05 d 0.705 0.020 17.91 0.51 e 0.291 - 0.299 7.39 - 7.59 e 0.050 0.006 1.27 0.15 e 1 0.376 nom. 9.40 nom. h e 0.394 - 0.417 10.01 - 10.60 l 0.036 0.008 0.91 0.20 l e 0.055 0.008 1.40 0.20 s 0.043 max. 1.09 max. y 0.004 max. 0.10 max. 0 - 10 0 - 10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surfac e mount pad pitch design reference only. 4. dimension s includes end flash. free datasheet http:///
SH69P26 42 p-dip 32-pin outline dimensions unit: inches/mm 1 32 e 1 s a 2 a l e e a d c b 1 b a 1 base plane seating plane 16 17 e 1 symbol dimensions in inches dimensions in mm a 0.210 max. 5.33 max. a 1 0.010 min. 0.25 min. a 2 0.155 0.010 3.94 0.25 0.018+ 0.004 0.46+ 0.10 b - 0.002 - 0.05 0.050+ 0.004 1.27+ 0.10 b 1 - 0.002 - 0.05 0.010+ 0.004 0.25+ 0.11 c - 0.002 - 0.05 d 1.650 typ. (1.670 max.) 41.91 typ. (42.42 max.) e 0.600 0.010 15.24 0.25 e 1 0.550 typ. (0.562 max.) 13.97 typ. (14.27 max.) e 1 0.100 0.010 2.54 0.25 l 0.130 0.010 3.30 0.25 0 - 15 0 - 15 e a 0.655 0.035 16.64 0.89 s 0.090 max. 2.29 max. notes: 1. the maximum value of dimension d includes end flash. 2. dimension e 1 does not include resin fins. 3. dimension s includes end flash. free datasheet http:///
SH69P26 43 data sheet revision history version content date 2.2 delete bonding diagram, pad location and upd ate dc electrical char acteristic feb. 2008 2.1 package information update apr. 2007 2.0 add reset pin share function (share as io) feb. 2006 1.0 original sep. 2005 free datasheet http:///

▲Up To Search▲

Price & Availability of SH69P26

	To Download SH69P26 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .